Memory devices, such as quad data rate static random access memories (SRAMs) can latch address values on both rising and falling edges of a timing clock for high speed, high throughput operations.
FIG. 10A is a timing diagram showing bank accesses for a conventional quad data rate SRAM device. FIG. 10A has waveforms for a timing clock CK, latched address values ADD, and operations within banks (Internal Ops). Letters “R” and “W” shown above waveform CK indicate the application of read and write commands. Letters “R” and “W” above the Internal Ops waveforms show the type of bank access executed within a bank.
Referring to FIG. 10A, at time t0, a read command can be received for an address in one bank (BNKA) on a rising edge of CK. At time t1, in response to the read command at time t0, the bank (BankA) can be accessed for a read operation.
Referring still to FIG. 10A, at time t2 a write command can be received for an address in another bank (BNKB) on a falling edge of CK. Such a write operation is not executed until a subsequent cycle (at time t6).
At time t3, another read command can be received on the next rising edge of CK. At time t4, the corresponding bank (BankC) can be accessed for the read operation.
At time t5, another write command can be received.
At time t6, a write operation in BankB can be performed in response to the bank address latched at time t2.
It is noted that in operations performed at the access speeds shown in FIG. 10A, there are no restrictions on bank addresses, as there is sufficient time between received commands (R and W of CK), as compared to the time needed to execute read and write operations within a bank (consecutive read and write operation of INTERNAL OPs).
FIG. 10B is a timing diagram showing bank accesses for a conventional quad data rate SRAM device, like that of FIG. 10A, but at a higher clock speed. FIG. 10B shows the same waveforms as FIG. 10A.
Referring to FIG. 10B, at time t3, a read operation can be executed in the bank latched at time t2. However, in the same general time period, a write operation to a BankX is being performed in response to a write command to BankX, issued in a previous clock cycle. Accordingly, the write operation to BankX and the read operation to BankC overlap one another.
Similarly, at time t5, the read operation to BankE (corresponding to BNKE latched at time t4) overlaps the write operation to BankB (corresponding to BNKB latched at time t1, in a previous cycle). At time at time t7, the read operation to BankG (corresponding to BNKG latched at time t6) overlaps the write operation to BankD (corresponding to BNKD latched at time t3, in a previous cycle).
To ensure proper operations, restrictions are placed on bank addresses so that the same bank is not subject to the overlapping read and write operations. Accordingly, as shown in FIG. 10B, BankC is restricted to not being the same as BankX (BankC !=BankX). Similarly, BankE !=BankB and BankG !=BankD.
Conventionally, to ensure such bank restrictions are maintained, a memory device can compare a read bank address (received on a rising edge of CK) to write bank addresses received in a previous clock cycle.
FIG. 10C shows a further restriction on a high speed memory device like that of FIG. 10B. FIG. 10C is a timing diagram showing how a write bank address can be switched in a conventional quad data rate SRAM. FIG. 10C shows the same waveform as FIG. 10B; however, unlike FIG. 10B, after the write to BankB at time t0, it is desired to switch to a new bank (BankF).
To ensure sufficient time is provided for comparing addresses, a “no operation” (NOP) cycle is inserted between times t2 and t3. It is understood that the access to BankF is delayed due to the insertion of the NOP cycle until time t7.
At time t4, following the NOP cycle, a read operation can be to any bank, as there is no possible overlapping write operation. Following time t4, read and write operations can continue as described, but with restrictions being based on the new write bank (BankF) received at time t1.
Accordingly, in response to a read operation at time t6, the corresponding BankD can be accessed for a read operation, but such a bank must be different from BankF, being accessed in response to the new write bank received at time t1.